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LSI Logic Corp. (Quote) today announced the availability of a System Packet Interface Level 4 (SPI-4) Phase 2 intellectual-property (IP) core, targeted for communications and storage markets.
System-level designs based on the company's SPI-4 Phase 2 core will allow designers to architect their ASICs with verified interoperability, significantly simplifying interface design and reducing time-to-market of high speed networking applications, officials said.
The SPI-4 Phase 2 core operates up to 800 MHz and allows the implementation of 12.8 Gbps throughput on the system bus. The core has been optimized for use in emerging applications requiring 10-Gbit Ethernet, OC-192 SONET and Packet-over-SONET (PoS).
"LSI Logic understands that its customers need complete solutions that are scalable, versatile, and reliable," said Tom Sandoval, vice president of LSI Logic Communications Marketing. "Having the SPI-4 Phase 2 core in our rich CoreWare library provides networking system architects the intellectual property they need to satisfy the explosive growth of Gigabit Ethernet and optical networking equipment requirements and has proven critical for helping them manage their increasing time to market pressures."
With LSI Logic's SPI-4 Phase 2 core and the company's proven CoreWare methodology, designers can rapidly meet stringent time-to-market requirements and develop SPI-4 Phase 2 based ASICs, officials said. The CoreWare design program provides a complete set of deliverables to ensure successful integration of intellectual property (IP) building blocks into complex ASICs or system-on-a-chip designs. It has made core reuse a reality through a design methodology that is optimized for an ASIC design environment.
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